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74LCX162373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor
February 2001 Revised August 2001
74LCX162373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor
General Description
The LCX162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LCX162373 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The 26 series resistor in the output helps reduce output overshoot and undershoot. The LCX162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
I 5V tolerant inputs and outputs I 2.3V-3.6V VCC specifications provided I Equivalent 26 series resistor outputs I 6.2 ns tPD max (VCC = 3.3V), 20 A ICC max I Power down high impedance inputs and outputs I Supports live insertion/withdrawal (Note 1) I 12 mA output drive (VCC = 3.0V) I Implements patented noise/EMI reduction circuitry I Latch-up performance exceeds 500 mA I ESD performance: Human body model > 2000V Machine model > 200V I Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX162373GX (Note 2) 74LCX162373MEA (Note 3) 74LCX162373MTD (Note 3) Package Number BGA54A (Preliminary) MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500443
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74LCX162373
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn LEn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 LE1 NC VCC GND GND GND VCC NC LE2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs Pin Assignment for FBGA LE1 X H H L OE1 H L L L Inputs LE2 X H (Top Thru View) H L OE2 H L L L I8-I15 X L H X I0-I7 X L H X Outputs O0-O7 Z L H O0 Outputs O8-O15 Z L H O0
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
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74LCX162373
Functional Description
The LCX162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LCX162373
Absolute Maximum Ratings(Note 4)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 5) VI < GND VO < GND VO > VCC V mA mA mA mA mA
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150
C
Recommended Operating Conditions (Note 6)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 12 Units V V V
8 4 -40
0 85 10
mA
C
ns/V
t/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -4 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 4 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II IOZ Input Leakage Current 3-STATE Output Leakage 0 VI 5.5V 0 VO 5.5V VI = VIH or VIL Conditions VCC (V) 2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6 2.3 - 3.6 2.3 2.7 3.0 2.7 3.0 2.3 - 3.6 2.3 2.7 3.0 2.7 3.0 2.3 - 3.6 2.3 - 3.6 VCC - 0.2 1.8 2.2 2.4 2.0 2.0 0.2 0.6 0.4 0.55 0.6 0.8 5.0 5.0 A A V V TA = -40C to +85C Min 1.7 2.0 0.7 0.8 Max Units V V
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74LCX162373
DC Electrical Characteristics
Symbol IOFF ICC ICC Parameter Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input
(Continued)
VCC (V) 0 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 TA = -40C to +85C Min Max 10 20 20 500 A A A
Conditions VI or VO = 5.5V VI = V CC or GND 3.6V VI, VO 5.5V (Note 7) VIH = VCC -0.6V
Units
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time, In to LE Hold Time, In to LE LE Pulse Width Output to Output Skew (Note 8) Output Disable Time Propagation Delay In to On Propagation Delay LE to On Output Enable Time 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 1.0 1.0 Max 6.2 6.2 6.3 6.3 6.9 6.9 6.0 6.0 VCC = 2.7V CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 Max 6.7 6.7 7.2 7.2 7.3 7.3 6.3 6.3 VCC = 2.5V 0.2V CL = 30 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 Max 7.4 7.4 7.6 7.6 9.0 9.0 7.2 7.2 ns ns ns ns ns ns ns ns Units
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25C Typical 0.35 0.25 -0.35 -0.25 Units V V
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF
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74LCX162373
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC = 3.3 0.3V, and 2.7V VCC x 2 at VCC = 2.5 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
trise and tfall
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74LCX162373
Schematic Diagram Generic for LCX Family
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74LCX162373
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary
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74LCX162373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LCX162373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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